The present invention relates in general to the field of integrated circuits, and more particularly, to the fabrication of semiconductor integrated circuit components such as a dynamic random access memory cell, and especially the cell""s capacitor.
Without limiting the scope of the invention, its background is described in connection with dynamic access random memory (DRAM) cells, as an example.
As is well known in the art of integrated circuit design, layout and fabrication, the manufacturing cost of a given integrated circuit is largely dependent upon the chip area required to implement desired functions. The chip area is defined by the geometries and sizes of the active components disposed in the wafer substrate. Active components include gate electrodes in metal-oxide semiconductors (MOS) and diffused regions such as MOS source and drain regions and bipolar emitters, collectors and base regions. These geometries and sizes are often dependent upon the photolithographic resolution available for the particular equipment used for processing the integrated circuit.
A significant problem of current techniques for the formation of integrated circuit structures as applied to very-large-scale integration (VLSI) as more and more layers are added, is that additional steps add additional complexities to the creation of circuits on the wafer surface. The resolution of small image sizes in photo-lithography becomes more difficult due to light reflection and the thinning of the photoresist during processing. In addition, the smaller patterns lead to increasing difficulties in the electrical isolation of the circuits. As the circuits shrink, the capacitor, can become larger than the underlying circuitry, and thus the determining factor in the cell size, thereby requiring the capacitors to be stacked.
As a two dimensional process used to achieve a three dimensional structure, the goal of photolithographic patterning is to establish the horizontal and vertical dimensions of the various devices and circuits used to create a pattern that meets design requirements, such as, the correct alignment of circuit patterns on the wafer surface. As line widths shrink, photolithography of patterns down to the nanometer level and smaller approach the limits of resolution of present equipment. These width lines, in the nanometer range, become increasingly more difficult to pattern because of the need to isolate the integrated circuit components.
A DRAM cell generally consists of a transistor and a capacitor. A bitline is connected to one of the transistor source/drains and a wordline to its gate, with the other source/drain being connected to the capacitor. As the density of DRAM cells on a silicon chip increases, DRAM cells having three dimensional structures, such as stacked capacitors, have been developed to meet the increased need for miniaturization. The use of stacked three dimensional structures, for example, allows the DRAM designer to maximize the capacitance of storage nodes within the limited area of the DRAM cell.
What is needed is a structure and method for using current integrated circuit processing techniques and manufacturing equipment that meet the demands of VLSI integrated circuits. One particular area in need of improvement is the fabrication of capacitors, and more particularly stack or crown capacitors, e.g., stack capacitors used in DRAM cells. As the circuits shrink, the capacitor can become larger than the underlying circuitry, and thus the determining factor in the cell size, thus the need for stack capacitors. The capacitor and cell designs must conform to current equipment and manufacturing techniques, and at the same time, provide the required increase in chip capacity and reliability.
Unlike flatplate capacitors of the prior art, crown capacitors are three-dimensional and it is recognized herein that in the past, during some stage of fabrication, some of the partially constructed capacitors could be subjected to underetching due, e.g., to inherent variations in etching across the wafer which can remove part of the support of those capacitors and thus subject those partially constructed capacitors to damage during subsequent processing. Our recognition of this problem has led us to the process modification described herein, which significantly improves the support of the partially fabricated capacitor and significantly improves circuit yields.